1. Field of the Invention
The present invention relates to a band gap (or bandgap) circuit based on a switched-capacitor technique.
2. Description of the Related Art
A band gap circuit is commonly used in analog integrated circuits (ICs) and complementary metal oxide semiconductor (CMOS) analog circuits as a reference-voltage circuit. The band gap circuit generates a constant reference voltage that is independent of temperature and power source voltage.
However, a band gap circuit utilizes a potential of a forward biased positive-negative (p-n) junction that has a negative temperature-dependency. In other words, the potential decreases as temperature increases. Therefore, a voltage that is proportional to absolute temperature (PTAT) is added to generated reference voltage to obtain a reference voltage that is independent of temperature.
The band gap circuits based on a switched capacitor technique (hereinafter, “switched-capacitor band gap circuit”) are known in the art. In the switched-capacitor band gap circuit, a capacitance ratio is used to obtain a desirable PTAT voltage by multiplying a thermal voltage k·T/q by a coefficient, where q is an electrical charge of electrons, k is the Boltzmann constant, and T is absolute temperature. In an integrated circuit, the capacitance ratio can be obtained at the highest accuracy. Therefore, in the switched-capacitor band gap circuit, which uses the capacitance ratio, a desirable PTAT voltage can be obtained with high accuracy based on the thermal voltage. In other words, switched-capacitor band gap circuits can generate highly accurate reference voltage.
A switched-capacitor band gap circuit shown in FIG. 1 has been disclosed in, for example, U.S. Pat. No. 5,563,504. In the conventional switched-capacitor band gap circuit, an emitter of a positive-negative-positive (PNP) bipolar transistor Q1 is connected to a noninverting input (+) of an operational amplifier circuit OP1. A base and a collector of the PNP bipolar transistor Q1 are connected to a ground GND. An inverting input (−) of the operational amplifier circuit OP1 is connected to the ground GND via a capacitor C1.
The inverting input (−) is connected to an output of the operational amplifier circuit OP1 via a capacitor C2. A switch S1 is connected in parallel with the capacitor C2. A current source I1 is connected to the emitter of the bipolar transistor Q1 and a current source I2 is coupled between the emitter of the bipolar transistor Q1 and a positive power source Vdd via a switch S2.
The current sources I1 and I2 output currents I1 and I2 respectively. The capacitors C1 and C2 have capacitances C1 and C2 respectively. Vo is an output reference potential of the operational amplifier circuit OP1. N1 and N2 are nodes.
When a base-to-emitter voltage, which is a forward bias voltage at the p-n junction, is Vbe, a relationship between Vbe and absolute temperature T is expressed asVbe=Veg−a·T  (1)where Veg is a band gap voltage (approximately 1.2 volts (V)) of silicon, and a is temperature dependency (approximately 2 mV/° C.) of Vbe.
Furthermore, a relationship between a current I of the emitter, which is a current of a diode, and Vbe is expressed asI=I0 exp(q·Vbe/k·T)  (2)where q is an electrical charge of electrons, and k is the Boltzmann constant.
As shown in FIG. 1, at the beginning, the switch S1 is closed and the switch S2 is open. Since the switch S1 is closed, a potential of the node N2 is equal to an output potential of the operational amplifier circuit OP1. In addition, since the switch S2 is open, the current I1 flows through the PNP bipolar transistor Q1. A potential of the node N2 is Vbe1 when the base-to-emitter voltage is Vbe1. Consequently, an electrical charge that can be accumulated at the node N2 while the switch S1 is closed is C1×Vbe1.
Then, the switch S1 is opened and the switch S2 is closed. As the switch S1 is open, the electrical charge of the node N2 is conserved. In addition, currents flow into the PNP bipolar transistor Q1 from both of the current sources I1 and I2. Thus, the current flowing through the PNP bipolar transistor Q1 increases from I1 to I1+I2, and the potential of the node N1 increases.
When I1+I2=m·I1 where m is a coefficient, relationships between I1 and Vbe1, and between I2 and Vbe2 are expressed asI1=I0 exp(q·Vbe1/k·T)  (3)m·I1=I0 exp(q·Vbe2/k·T)  (4)where the base-to-emitter voltage when the current m·I1 flows through the PNP bipolar transistor Q1 is Vbe2.
By performing division on Equation 3 and Equation 4, the following Equation 5 is obtained.m=exp(q·Vbe2/k·T−qVbe1/k·T)  (5)When Equation 5 is solved for ΔVbe assuming Vbe2−Vbe1=ΔVbe, Equation 6 is obtained.ΔVbe=(k·T/q)ln(m)  (6)
The potential of the node N1 increases by ΔVbe from Vbe1 to be Vbe2. Therefore, if a gain of the operational amplifier circuit OP1 is sufficiently large, the potential of the node N2 also increases by ΔVbe to be Vbe2. An output potential of the operational amplifier circuit OP1 is determined to conserve the electrical charge of the node N2. As the potential of the node N2 increases, the electrical charge of the node N2 increases. The increased amount Δq1 is expressed asΔq1=C1·ΔVbe  (7)
On the other hand, if the output potential of the operational amplifier circuit OP1 increases, the electrical charge of the node N2 decreases. The decreased amount Δq2 is expressed asΔq2=C2(ΔVo−ΔVbe)  (8)where the increased amount in the output potential of the operational amplifier circuit OP1 is ΔVo.
Since Δq1 and Δq2 are equal to each other, the following Equation 9 is obtained.C1·ΔVbe=C2(ΔVo−ΔVbe)  (9)When Equation 9 is solved for ΔVo, Equation 10 is obtained.ΔVo=ΔVbe+(C1/C2)ΔVbe  (10)
Consequently, the output reference potential Vo of the operational amplifier circuit OP1 is finally obtained by the following Equation 11.
                                                        Vo              =                              Vbe1                ⁢                                                                  +                                  Δ                  ⁢                                                                          ⁢                  Vbe                                +                                                                            (                                              C                        ⁢                                                                                                  ⁢                                                  1                          /                          C                                                ⁢                                                                                                  ⁢                        2                                            )                                        ·                    Δ                                    ⁢                                                                          ⁢                  Vbe                                                                                                        =                                                Vbe                  ⁢                                                                          ⁢                  2                                +                                                                            (                                              C                        ⁢                                                                                                  ⁢                                                  1                          /                          C                                                ⁢                                                                                                  ⁢                        2                                            )                                        ·                    Δ                                    ⁢                                                                          ⁢                  Vbe                                                                                        (        11        )            
The forward bias voltage Vbe2 at the p-n junction has a negative temperature-dependence as shown in Equation 1. On the other hand, ΔVbe increases in proportion to temperature as shown in Equation 6. Therefore, by setting C1/C2 at an appropriate value, the circuit can be designed so as to obtain the output reference potential Vo independent of temperature. In such a condition, Vo corresponds to a band gap voltage of silicon, and is 1.2 V. Thus, in the circuit shown in FIG. 1, it is possible to obtain a reference voltage independent of temperature by appropriately setting the circuit constant.
A circuit shown in FIG. 2 is also an example of the conventional switched-capacitor band gap circuit. As shown in FIG. 2, an emitter of a PNP bipolar transistor Q2 is connected to a noninverting input (+) of an operational amplifier circuit OP2. A base and a collector of the PNP bipolar transistor Q2 are connected to the ground GND. Moreover, an emitter of a PNP bipolar transistor Q3 is connected to an inverting input (−) of the operational amplifier circuit OP2 through a capacitor C3. A base and a collector of the PNP bipolar transistor Q3 are connected to the ground GND.
The noninverting input (+) of the operational amplifier circuit OP2 is connected to a switch S3. A capacitor C4 is coupled between the switch S3 and the inverting input (−). A switch S4 is coupled between an output of the operational amplifier circuit OP2 and the capacitor C4. A switch S5 is coupled between the output and the inverting input (−). A current sources I1 and nI1 are coupled through switches S6 and S7 respectively, between the positive power source Vdd and each of the emitters of the PNP bipolar transistor Q2 and Q3.
In the following explanation of an operation of the band gap circuit shown in FIG. 2, I1 and nI1 represent currents of the current sources I1 and nI1, C3 and C4 represent capacitances of the capacitors C3 and C4, and Vo represents an output reference potential of the operational amplifier circuit OP2. Nodes between an internal circuit and each of the noninverting input (+), the emitter of the PNP bipolar transistor Q3, and the inverting input (−) are nodes N3, N4, and N5 respectively. A node between the capacitor C4 and both of the switches S3 and S4 is a node N6. Sizes of the PNP bipolar transistors Q2 and Q3 are equal to each other.
As shown in FIG. 2, at the beginning, the switch S6 is closed on a side of the PNP bipolar transistor Q2, and the switch S7 is closed on a side of the PNP bipolar transistor Q3. The switches S3 and S5 are closed, and the switch S4 is open. The current I1 flows through the PNP bipolar transistor Q2. A base-to-emitter voltage of the PNP bipolar transistor Q2 is Vbe1. The current nI1 flows through the PNP bipolar transistor Q3. A base-to-emitter voltage of the PNP bipolar transistor Q3 is Vbe2.
Since the switch S3 is closed, a potential at the node N6 is Vbe, which is equal to a potential of the node N3. Moreover, since the switch S5 is close, a potential of the node N5 is approximately Vbe1, which is substantially equal to the potential of the node N3. It is assumed that an ideal condition in which an offset voltage becomes zero in the operational amplifier circuit OP2 is obtained. Because a potential of the node N4 is Vbe2, an electrical charge to be accumulated in the capacitor C3 is −(Vbe2−Vbe1)C3. In addition, since the potentials of the nodes N5 and N6 are equal to each other, an electrical charge to be accumulated in the capacitor C4 becomes zero. Therefore, an electrical charge to be accumulated in the node N5 is −(Vbe2−Vbe1)C3.
When the switch S5 is switched to be open in this condition, the electrical charge accumulated in the node N5 is conserved. Then, the switch S3 is switched to be open, the switch S6 is switched to be closed on a side of the PNP bipolar transistor Q3, and the switch S7 is switched to be closed on a side of the PNP bipolar transistor Q2. Furthermore, the switch S4 is switched to be closed. Thus, the current nI1 flows through the PNP bipolar transistor Q2. Therefore, the base-to-emitter voltage of the PNP bipolar transistor Q2 becomes Vbe2. On the other hand, the current I1 flows through the PNP bipolar transistor Q3. Therefore, the base-to-emitter voltage of the PNP bipolar transistor Q3 becomes Vbe1.
Since the potential of the node N3 becomes Vbe2, if a voltage gain of the operational amplifier circuit OP2 is enough large, the potential of the node N5 also becomes Vbe2. An output potential of the operational amplifier circuit OP2 is determined to conserve the electrical charge of the node N5. The electrical charge qN5 of the node N5 is expressed asqN5=C3(Vbe2−Vbe1)−(Vo−Vbe2)C4  (12)where Vo is output potential.
As described above, the electrical charge of the node N5 before each of the switches is switched is −(Vbe2−Vbe1)C3. Based on this, the following Equation 13 is obtained.−(Vbe2−Vbe1)C3=C3(Vbe2−Vbe1)−(Vo−Vbe2)C4  (13)
When Equation 13 is solved for Vo where Vbe2−Vbe1=ΔVbe, the following Equation 14 is obtained.Vo=Vbe2+ΔVbe×2C3/C4  (14)
In the circuit designed such that ΔVbe is generated depending on a predetermined current ratio, ΔVbe has dependency that is proportional to the absolute temperature T. Therefore, with the circuit shown in FIG. 2, it is possible to obtain a reference voltage independent of temperature by appropriately setting the circuit constant, similarly to the case with the circuit shown in FIG. 1.
Various other switched-capacitor band gap circuits are know in the art. A circuit disclosed in, for example, Japanese Patent Application Laid-Open No. H5-181556 is configured as follows. The circuit includes a first current source and a first diode element, a second current source and a second diode, a first switch, a second switch, a first capacitor, a second capacitor, a third switch, an amplifier, a fourth switch, and a third capacitor. The first current source and the first diode element are joined at a first node and connected in series between a first and a second voltage terminals. The second current source and the second diode element are joined at a second node and connected in series between the first and the second voltage terminals. The first and the second current sources have different currents. The first switch includes a first terminal selectively connectable to a second and a third terminals thereof. The second switch is selectably connected to a first, a second, and a third terminals. The second and third terminals are connected respectively to the second node and the second voltage terminal. The first capacitor includes a first terminal that is connected to the first terminal of the first switch. The second capacitor includes a first terminal that is connected to the first terminal of the second switch. Second terminals of the first and the second capacitors are connected in common to a third node. The third switch includes a first and a second terminals. The first terminal of the third switch is connected to the third node. The amplifier includes an input and an output, and the input is connected to the second terminal of the third switch. The fourth switch includes a first and a second terminals connected between the input and the output of the amplifier. The third capacitor includes a first terminal connected to the input of the amplifier and a second terminal connected to the output of the amplifier.
A circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-154749 is configured as follows. The circuit includes a band gap circuit, a switched capacitor circuit, and a filter. The band gap circuit outputs a bandgap output voltage from a first output terminal. The switched capacitor circuit operates in response to a control clock. The filter receives the bandgap output voltage, and outputs received bandgap output voltage to a second output terminal. The bandgap output voltage is controlled based on a frequency of the control clock.
A circuit for generating a reference voltage independent of temperature disclosed in, for example, Japanese Patent Application Laid-Open No. S58-500045 is configured as follows. The circuit includes a first and a second bipolar transistors, a clock, a first and a second switched capacitors, and an amplifier. The first and the second bipolar transistors have a predetermined base voltage. The first and the second bipolar transistors are biased to different current density, and generate a first emitter voltage and a second emitter voltage at each emitter. The clock generates a first and a second clock signals that do not overlap with each other. The first switched capacitor is coupled to the base voltage in response to the first clock signal, is coupled to the first emitter voltage in response to the second clock signal, and generates a first electrical charge relating to Vbe of the first bipolar transistor. The second switched capacitor is couple to the second emitter voltage in response to the first clock signal, is couple to the first emitter voltage in response to the second clock signal, and generates a second electrical charge relating to a difference between Vbe of the first bipolar transistor and Vbe of the second bipolar transistor. The amplifier is connected to the first and the second switched capacitors, and generates a reference voltage that is proportional to a sum of the first electrical charge and the second electrical charge. Such conventional circuit is also disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 33, No. 7, 1998, pp. 1117-1122 titled “A Switched-Current, Switched-Capacitor Temperature Sensor in 0.6− μm CMOS” by Mike Tuthill.
As described above, in the conventional switched-capacitor band gap circuit, in multiplying the thermal voltage k·T/q by a predetermined coefficient, a capacitance ratio of a switched capacitor, for example, C1/C2 in Equation 11 and C3/C4 in Equation 14, is used as the coefficient. Generally, to obtain the capacitance ratio with high accuracy and high reproducibility in an IC, plural units of capacitors each of which has a predetermined unit capacitance are prepared. A desirable capacitance ratio is obtained by adjusting a ratio in the number of such capacitors. Therefore, the capacitance ratio, which is the coefficient, is an integer ratio. To approximate the integer ratio to a desirable coefficient, it is preferable that the integer ratio can be set more precisely. To set the integer ratio in detail, however, it is necessary to increase the number of such capacitors. The capacitors disadvantageously occupy silicon area.